Semiconductor device, fabrication method for semiconductor device, power supply apparatus and high-frequency amplifier

ABSTRACT

A semiconductor device is configured including a p-type back barrier layer provided over a substrate and formed front a p-type nitride semiconductor in which Mg or Zn is doped, a nitride semiconductor stacked structure provided over the p-type back barrier layer, the nitride semiconductor stacked structure including an electron transit layer and an electron supply layer, a source electrode, a drain electrode and a gate electrode provided over the nitride semiconductor stacked structure, and a groove extending to the p-type back barrier layer.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based, upon and claims the benefit of priority ofthe prior Japanese Patent Application No. 2015-043667, filed on Mar. 5,2015, the entire contents of which are incorporated herein by reference.

FIELD

The embodiments discussed herein are related to a semiconductor device,a fabrication method for a semiconductor device, a power supplyapparatus and a high-frequency amplifier.

BACKGROUND

Since a nitride semiconductor has a characteristic in high saturationelectron velocity, wide band gap and so forth, application of thenitride semiconductor to a semiconductor device of a high withstandvoltage and high output power is examined.

For example, the band gap of GaN that is a nitride semiconductor isapproximately 3.4 eV, and is greater than the band gap of Si(approximately 1.1 eV) and the band gap of GaAs (approximately 1.4 eV)and has a high breakdown field strength. Therefore, GaN is a veryprospective material as a material for a semiconductor device forachieving high voltage action and high output power,

As a semiconductor device for which a nitride semiconductor is used, afield-effect transistor, particularly, a high electron mobilitytransistor (HEMT), is available.

For example, as a GaN-based HEMT (GaN-HEMT), an AlGaN/GaN-HEMT for whichGaN and AlGaN are used as an electron transit layer (channel layer) andan electron supply layer, respectively, is available. In theAlGaN/GaN-HEMT, a distortion arising from a lattice constant differencebetween GaN and AlGaN occurs with AlGaN, and high-concentrationtwo-dimensional electron gas (2DEG) is obtained by piezoelectricpolarization and a spontaneous polarization difference of AlGaN causedby the distortion. Therefore, a high-withstand-voltage and high-outputpower device can be implemented by the AlGaN/GaN-HEMT.

SUMMARY

According to an aspect of the embodiment, a semiconductor devicecomprises a p-type back barrier layer provided over a substrate andformed from a p-type nitride semiconductor in which Mg or Zn is doped, anitride semiconductor stacked structure provided over the p-type backbarrier layer, the nitride semiconductor stacked structure including anelectron transit layer and an electron supply layer, a source electrode,a drain electrode and a gate electrode provided over the nitridesemiconductor stacked structure, and a groove extending to the p-typeback barrier layer.

According to an aspect of the embodiment, a power supply apparatuscomprises a transistor, wherein the transistor includes a p-type back,barrier layer provided over a substrate and formed from a p-type nitridesemiconductor in which Mg or Zn is doped, a nitride semiconductorstacked structure provided over the p-type back barrier layer, thenitride semiconductor stacked structure including an electron transitlayer and an electron supply layer, a source electrode, a drainelectrode and a gate electrode provided over the nitride semiconductorstacked structure, and a groove extending to the p-type back barrierlayer.

According to an aspect of the embodiment, a high-frequency amplifiercomprises an amplifier to amplify an input signal, the amplifier toinclude a transistor, the transistor including a p-type back barrierlayer provided over a substrate and formed from a p-type nitridesemiconductor in which Mg or Zn is doped, a nitride semiconductorstacked structure provided over the p-type back barrier layer, thenitride semiconductor stacked structure including an electron transitlayer and an electron supply layer, a source electrode, a drainelectrode and a gate electrode provided over the nitride semiconductorstacked structure, and a groove extending to the p-type back barrierlayer.

According to an aspect of the embodiment, a fabrication method for asemiconductor device comprises forming a p-type back barrier layer froma p-type nitride semiconductor in which Mg or Zn is doped over asubstrate, forming a nitride semiconductor stacked structure includingan electron transit layer and an electron supply layer over the p-typeback barrier layer, forming a source electrode, a drain electrode and agate electrode over the nitride semiconductor stacked structure, forminga groove extending to the p-type back barrier layer, and performing ananneal process for desorbing hydrogen from the p-type back barrier layerthrough the groove to activate the p-type back barrier layer.

The object and advantages of the invention will be realized and attainedby means of the elements and combinations particularly pointed out inthe claims. It is to be understood that both the foregoing generaldescription and the following detailed description are exemplary andexplanatory and are not restrictive of the invention.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a schematic sectional view depicting a configuration of asemiconductor device according to a first embodiment;

FIGS. 2A to 2E are schematic sectional views illustrating a fabricationmethod for a semiconductor device according to the first embodiment;

FIGS. 3A and 3B are schematic views depicting a configuration of asemiconductor device according to a first modification to the firstembodiment, wherein FIG. 3A is a sectional view and FIG. 3B is a topplan view;

FIGS. 4A to 4D are schematic sectional views illustrating a fabricationmethod for a semiconductor device according to the first modification tothe first embodiment;

FIG. 5 is a schematic sectional view depicting a configuration of asemiconductor device according to a second modification to the firstembodiment;

FIGS. 6A to 6D are schematic sectional views illustrating a fabricationmethod for a semiconductor device according to the second modificationto the first embodiment;

FIG. 7 is a schematic sectional view illustrating a fabrication methodfor a semiconductor device according to a third modification to thefirst embodiment;

FIGS. 8A to 8E are schematic sectional views illustrating a fabricationmethod for a semiconductor device according to the third modification tothe first embodiment;

FIG. 9 is a view illustrating a subject of the present invention and isa schematic sectional view depicting a configuration of anAlGaN/GaN-HEMT having a p-GaN back barrier layer,

FIGS. 10A and 10B are views illustrating a subject of the present,invention, wherein FIG. 10A is a view depicting a relationship between aposition in a thicknesswise direction and a potential of a normalAlGaN/GaN-HEMT (normal structure) and an AlGaN/GaN-HEMT having a p-GaNback barrier layer (p-GaN back barrier structure) and FIG. 10B is a viewdepicting a stacked structure of the normal structure and the p-GaN backbarrier structure in an associated relationship with the thicknesswisedirection position of FIG. 10A;

FIG. 11 is a view illustrating a subject of the present invention and isa view depicting a result when an activation anneal process is performedfor an AlGaN/GaN-HEMT having a p-GaN back barrier layer and a remainingH concentration in the p-GaN back barrier layer is measured;

FIG. 12 is a schematic top plan view depicting a configuration of asemiconductor device (semiconductor package) according to a secondembodiment;

FIG. 13 is a schematic view depicting a configuration of a PFC circuitincluded in a power supply apparatus according to the second embodiment;and

FIG. 14 is a schematic view depicting a configuration of ahigh-frequency amplifier according to a third embodiment.

DESCRIPTION OF EMBODIMENTS

Incidentally, in order to suppress leak current flowing between a sourceelectrode and a drain electrode where the gate length is short, it seemsa possible idea to provide a p-GaN back barrier layer under a GaNchannel layer, for example, as depicted in FIG. 9. By providing thep-GaN back barrier layer, the potential under the GaN channel layer canbe increased as depicted in FIGS. 10A and 10B, and therefore, the leakcurrent flowing between the source electrode and the drain electrode canbe suppressed.

If Mg operating as an accepter is coupled with H existing in crystal inthe p-GaN back barrier layer, then positive holes cannot be generated.Therefore, where the p-GaN back barrier layer is provided, an activationanneal process for desorbing H thereby to cause Mg to function as anacceptor to activate the p-GaN back barrier layer is performed.

However, in the AlGaN/GaN-HEMT having the p-GaN back barrier layer, aGaN channel layer and an AlGaN electron supply layer exist over thep-GaN back barrier layer. Since positive fixed charge is generated on aninterface between the AlGaN electron supply layer and the GaN channellayer, an internal electric field is generated between the p-GaN backbarrier layer and the GaN channel layer. Therefore, it has been foundthat desorption of H from the surface of the p-GaN back barrier layer isinhibited and desorption of H from a side wall on which the p-GaN backbarrier layer is exposed, namely, activation, advances. Further, sincethe dispersion speed of H is low, it has been recognized that H isdesorbed little at a location spaced far from the side wall and it isdifficult to activate the entire p-GaN back barrier layer withcertainty.

It is to be noted that, while a subject where the p-GaN back barrierlayer is provided in the AlGaN/GaN-HEMT is described here, there is asimilar subject also in the case in which a p-type back barrier layerformed from a p-type nitride semiconductor in which Mg or Zn is doped isprovided in a semiconductor device that includes a nitride semiconductorstacked structure including an electron transit layer and an electronsupply layer.

Therefore, where a p-type back barrier layer formed from a p-typenitride semiconductor in which Mg or Zn is doped is provided in asemiconductor device that includes a nitride semiconductor stackedstructure including an electron transit layer and an electron supplylayer, it is demanded to activate the entire p-type back barrier layer.

In the following, a semiconductor device, a fabrication method for asemiconductor device, a power supply apparatus and a high-frequencyamplifier according to embodiments of the present invention aredescribed with reference to the drawings,

First Embodiment

First, a semiconductor device and a fabrication method for asemiconductor device according to a first embodiment are described withreference to FIGS. 1 to 8E.

The semiconductor device according to the present embodiment is acompound semiconductor device for which a compound semiconductor suchas, for example, a nitride semiconductor is used, and is a semiconductordevice that includes a nitride semiconductor stacked structure (HEMTstructure) including an electron transit layer and an electron supplylayer.

Here, the present embodiment is described taking, as an example, anAlGaN/GaN-HEMT in which GaN, AlGaN and p-GaN that is a p-type nitridesemiconductor are used for an electron transit layer (channel layer), anelectron supply layer and a p-type back barrier layer, respectively.

For example, as depicted in FIG. 1, the present semiconductor deviceincludes a nitride semiconductor stacked structure 6 including a GaNchannel layer 4 and an AlGaN electron supply layer 5 provided over asubstrate 1.

In this case, as indicated by a broken line in FIG. 1, two-dimensionalelectron gas (2DEG) is generated in the proximity of an interfacebetween the GaN channel layer 4 and the AlGaN electron supply layer 5.

Here, the substrate 1 is, for example, a SiC substrate. It is to benoted that one of a Si substrate, a SiC substrate, a sapphire substrate,a GaO substrate, an AlN substrate and a GaN substrate may be used forthe substrate 1.

Further, the present semiconductor device includes a p-GaN back barrierlayer 3 formed from p-GaN in which Mg is doped and provided under theGaN channel layer 4.

In this manner, the present semiconductor device

includes the p-GaN back barrier layer 3 provided over the substrate 1and further includes the nitride semiconductor stacked structure 6including the GaN channel layer 4 and AlGaN electron supply layer 5 andprovided over the p-GaN back barrier layer 3. Here, a structure isformed in which a buffer layer 2, the p-GaN back barrier layer 3, theGaN channel layer 4 and the AlGaN electron supply layer 5 are stacked onthe substrate 1.

A source electrode 7, a drain electrode 8 and a gate electrode 9 areprovided over the nitride semiconductor stacked structure 6.

Particularly, in the present embodiment, a groove 10 is provided so asto extend to the p-GaN back barrier layer 3. In particular, the groove10 extends from the surface of the nitride semiconductor stackedstructure 6 to the p-GaN back barrier layer 3. It is to be noted that,since the groove 10 is formed by etching as hereinafter described, thegroove 10 is an etching region. Further, as hereinafter described, thegroove 10 is used to desorb hydrogen (H) from the p-GaN back barrierlayer 3. Therefore, the groove 10 is referred to sometimes as hydrogendesorption groove,

Here, the groove 10 extends to the lower face of the p-GaN back barrierlayer 3, namely, to the upper face of the buffer layer 2, It is to henoted that the groove 10 is not limited to this, and the groove 10 mayextend to the upper face of the p-GaN back barrier layer 3, namely, tothe lower face of the GaN channel layer 4 or may extend to anintermediate position of the p-GaN back barrier layer 3 in athicknesswise direction,

Further, the groove 10 here is provided in an element isolation region11. In particular, the groove 10 is provided in the proximity of anactive region 12, namely, in the element isolation region 11 in theproximity of the active region 12. It is to be noted that the elementisolation region 11 is provided around the active region 12, and ispositioned at the inner side than a side wall 13 of a wafer or a chip.

Further, since the groove 10 here is formed by performing etching to thep-GaN back barrier layer 3 as hereinafter described, the entire GaNchannel layer 4 can be isolated physically. Therefore, as hereinafterdescribed, the element isolation performance can be enhanced incomparison with an alternative case in which ion implantation is onlyperformed, to the proximity of the AlGaN/GaN interface to form theelement isolation region 11.

Further, here, also a passivation film (here, SiN film) 14 for coveringthe surface is provided, and also the surface of the groove 10 iscovered with the passivation film 14.

Incidentally, such a groove 10 that extends to the p-GaN back barrierlayer 3 as described above is provided from the reason described in thefollowing.

For example, in an AlGaN/GaN-HEMT for a high frequency application, thegate length is set short in order to increase the operation frequency.However, in this case, a short channel effect occurs and leak currentflows between the source electrode and the drain electrode.

In order to suppress such leak current as just described, it seems apossible idea to provide a p-GaN back barrier layer under a GaN channellayer (for example, refer to FIG. 9). Since, by providing the p-GaN backbarrier layer, the potential under the GaN channel layer can be raised(for example, refer to FIGS. 10A and 10B), leak current flowing betweenthe source electrode and the drain electrode can be suppressed.

If Mg acting as an acceptor in such a p-GaN back barrier layer asdescribed above is coupled with H existing in crystal, then positiveholes cannot be generated. Therefore, where the p-GaN back barrier layeris provided, an activation anneal process for desorbing H and causing Mgto function as an acceptor and activate the p-GaN back barrier layer isperformed.

However, in the AlGaN/GaN-HEMT having the p-GaN back barrier layer, theGaN channel layer and the AlGaN electron supply layer exist on the p-GaNback barrier layer. Thus, since positive fixed charge is generated onthe interface between the AlGaN electron supply layer and the GaNchannel layer, an internal electric field is generated between the p-GaNback barrier layer and the GaN channel layer. Therefore, it has beenturned out that desorption of H from the surface of the p-GaN backbarrier layer is inhibited and desorption of H from, the side wall onwhich the p-GaN back barrier layer is exposed, namely, activation, isadvanced. Further, since the dispersion speed of H is low, it has beenturned out that H is little desorbed at a location spaced far from theside wail and it is difficult to activate the entire p-GaN back barrierlayer with certainty.

Here, as the activation anneal process, an anneal process at 700° C. wasperformed for 10 minutes, for example, in an O₂ atmosphere for theAlGaN/GaN-HEMT including the p-GaN back barrier layer, and the remainingH concentration in the p-GaN back barrier layer was measured. As aresult, such a result as depicted in FIG. 11 was obtained.

It has been turned out that H can little be desorbed at a distance of 1mm or more from the side wall as depicted in FIG. 11.

For example, even if the activation anneal process is performed for achip having a size of several millimeters square such as an MMIC, thep-GaN back barrier layer is little activated at a central location ofthe chip.

Therefore, by providing such a groove 10 extending to the p-GaN backbarrier layer 3 as described above and performing the activation annealprocess as hereinafter described, the entire p-GaN back barrier layer 3can be activated (made to p-type) with certainty. Therefore, such agroove 10 extending to the p-GaN back barrier layer 3 as described aboveis provided in the semiconductor device fabricated in such a manner ashereinafter described.

In this manner, by providing such a groove 10 extending to the p-GaNback barrier layer 3 as described above, desorption of H can befacilitated and the entire p-GaN back barrier layer 3 can be activatedwith certainty in the AlGaN/GaN-HEMT in which the GaN channel layer 4and the AlGaN electron supply layer 5 exist on the p-GaN back barrierlayer 3. Further, by the p-GaN back barrier layer 3 that is providedunder the GaN channel layer 4 and activated entirely, leak currentflowing between the source electrode 7 and the drain electrode 8 wherethe gate length is short can be suppressed. In particular, desorption ofH can be facilitated and the p-GaN back barrier layer 3 can be uniformlyactivated in a plane of a wafer or a chip, and the AlGaN/GaN-HEMT havinglow leak current can be implemented. Further, also the p-GaN backbarrier layer 3 at a central portion that is a location spaced far from,the side wall 13 of a chip having a size of several millimeters squaresuch as, for example, an MMIC can be activated with certainty.

Now, a fabrication method for a semiconductor device according to thepresent embodiment is described with reference to FIGS. 2A to 2E.

First, as depicted in FIG. 2A, an AlN nucleation layer as the bufferlayer 2 is grown on a SiC substrate 1 as a growth substrate so as toobtain a thickness of, for example, approximately 200 nm, for example,by a MOCVD method.

Then, a p-GaN back barrier layer 3 in which Mg as a p-type impurity isdoped with a concentration, for example, of approximately 5×10¹⁹ cm⁻¹ isgrown, for example, by a thickness of approximately 300 nm.

Then, a GaN channel layer 4 is grown, for example, by a thickness ofapproximately 300 nm.

Then, an AlGaN electron supply layer 5 formed, for example, fromAl_(0.2)Ga_(0.8)N is grown, for example, by a thickness of approximately20 nm.

Here, the growth temperature may be, for example, approximately 100° C.,and the pressure may be, for example, 50 mbar. Further, as source gas,for example, mixture gas of trimethyl aluminum gas, trimethyl galliumgas and ammonia gas may be used.

It is to he noted that, while the present embodiment is describedtaking, as an example, a case in which a MOCVD method is used as acrystal growth method for nitride semiconductor crystal, the embodimentis not limited to this and some other crystal growth method such as, forexample, an MBE method can be used,

The AlN nucleation layer as the buffer layer 2, p-GaN back barrier layer3, GaN channel layer 4 and AlGaN electron supply layer 5 are stacked onthe SiC substrate 1 in this manner. Consequently, the nitridesemiconductor stacked structure 6 including the GaN channel layer 4 andAlGaN electron supply layer 5 is formed over the p-GaN back barrierlayer 3.

Then, as depicted in FIG. 2B, an element isolation region 11 is formedby performing, for example, ion implantation of Ar. Here, the ionimplantation of Ar for formation of the element isolation region 11 maybe performed with energy of such a degree that ions reach the 2DEGregion of the interface between the AlGaN electron supply layer 5 andthe GaN channel layer 4.

Then, as depicted in FIG. 2C, a groove (etching region) 10 is formed inthe element isolation region 11 in the proximity of the active region 12so as to extend from the surface of the nitride semiconductor stackedstructure 6, namely, from the surface of the AlGaN electron supply layer5, to the p-GaN back barrier layer 3, for example, by etching usingchlorine-based gas.

After the groove 10 extending to the p-GaN back barrier layer 3 isformed in this manner, as the activation anneal process for desorbing Hfrom the p-GaN back barrier layer 3 to activate the p-GaN back barrierlayer 3, an anneal process is performed at approximately 750° C. forapproximately 10 minutes, for example, in a nitrogen atmosphere, In thiscase, since the groove 10 extending to the p-GaN back barrier layer 3 isformed, H (hydrogen) can be desorbed from the p-GaN back barrier layer 3through the groove 10. In particular, H (hydrogen) can be desorbed notonly through the side wall 13 of the wafer but also through the groove10 provided at the inner side than the side wall 13. Consequently, theentire p-GaN back barrier layer 3 can be activated with certainty alsoincluding a location spaced far from the side wall 13 of the wafer.Further, by the p-GaN back barrier layer 3 provided under the GaNchannel layer 4 and activated entirely, leak current flowing between thesource electrode 7 and the drain electrode 8 can be suppressed alsowhere the gate length is short.

Thereafter, as depicted in FIG. 2D, a SiN film having a thickness of,for example, approximately 50 nm is formed as a passivation film 14 forcovering the surface, for example, by a CVD method. Here, with the SiNfilm as the passivation film 14, also the surface of the groove 10extending to the p-GaN back barrier layer 3, namely, the surface of thegroove 10 used to desorb H from the p-GaN back barrier layer 3, iscovered.

Finally, as depicted in FIG. 2E, after the SiN film 14 at the locationsat which electrodes are to be formed is removed by etching using, forexample, fluorine-based gas, a source electrode 7, a drain electrode 8and a gate electrode 9 are formed on the surface of the nitridesemiconductor stacked structure 6 (here, on the surface of the AlGaNelectron supply layer 5).

The semiconductor device according to the present embodiment can befabricated in such a manner as described above.

Accordingly, with the semiconductor device and the fabrication methodaccording to the present embodiment, there is an advantage that, wherethe p-GaN back barrier layer 3 formed from p-GaN in which Mg is doped isprovided, the entire p-GaN back barrier layer 3 can be activated withcertainty.

It is to be noted that, while the present embodiment is describedtaking, as an example, the semiconductor device that includes the GaNchannel layer 4 and the AlGaN electron supply layer 5 and in which thep-GaN back barrier layer 3 formed from p-GaN in which Mg is doped isprovided, the invention is not limited to this. For example, the presentinvention can be applied also to any semiconductor device that includesa semiconductor stacked structure including an electron transit layer(channel layer) and an electron supply layer and in which a p-type backbarrier layer formed from a p-type nitride semiconductor in which Mg orZn is doped is provided, and an advantage is obtained that the entirep-type back barrier layer can be activated with certainty therewith.

In particular, the p-type nitride semiconductor for forming the p-GaNback barrier layer 3 is not limited to p-GaN, and, for example,In_(x)Al_(y)Ga_((1−x−y)))N (0≦x<1, 0≦y<1, 0<x+y≦1) may be used. At thistime, it is preferable to use GaN or InGaN in that a higher effect canbe obtained. Further, a material in which Mg is doped may not be used,and, for example, a material in which Zn is doped may be used.

Further, the nitride semiconductor stacked structure 6 including theelectron channel layer 4 and the electron supply layer 5 is not limitedto the nitride semiconductor stacked structure 6 including the GaNchannel layer 4 and the AlGaN electron supply layer 5. For example, forthe electron supply layer 5, In_(x)Al_(y)Ga_((1−x−y))N (0≦x<1, 0≦y<1,0<x+y≦1) can be used. At this time, it is preferable to useAl_(0.2)Ga_(0.8)N or In_(0.17)Al_(0.83)N. Further, the nitridesemiconductor stacked structure 6 may include a cap layer for which GaNor the like is used,

Further, while the element isolation region 11 in the embodimentdescribed above is formed by ion implantation, the embodiment is notlimited to this, and the element isolation region may be formed, forexample, by dry etching. Here, where the element isolation region isformed by dry etching, the element isolation region, becomes an etchingregion (element isolation groove). In this case, the groove 10 extendingto the p-GaN back barrier layer 3 of the embodiment described above mayfunction also as an element isolation groove. In particular, one groovemay function as both of the groove for activating the p-GaN back barrierlayer (etching region) and the groove for element isolation (etchingregion).

Further, while the groove 10 extending to the p-GaN back harrier layer 3in the embodiment described above is provided in the element isolationregion (inactive region) 11 in the proximity of the active region 12,the embodiment is not limited to this. For example, the groove extendingto the p-GaN back, barrier layer may be provided, in the active regionor in the proximity of the active region. This is because H in thep-type back barrier layer in the active region can be desorbed moreefficiently as the groove extending to the p-type back barrier layer isprovided at a position nearer to the active region.

For example, as depicted in FIGS. 3A and 3B, where the peripheral regionof the active region 12 is the inactive region (element isolationregion) 11, the groove (etching region) 10 extending to the p-type backbarrier layer 3 may be provided in the active region 12. In particular,where a plurality of source electrodes 7, drain electrodes 8 and gateelectrodes 9 are provided in parallel to each other in the active region12 and they are provided repetitively in order of the source electrode7, drain electrode 8 and gate electrode 9, the groove 10 extending tothe p-type back barrier layer 3 may be provided just under each of thesource electrodes 7. In this case, the groove 10 extending to the p-typeback barrier layer 3 is the groove 10 extending from the surface of thenitride semiconductor stacking structure 6 to the p-type back barrierlayer 3. Further, the source electrodes 7 are provided over the grooves10 extending to the p-type back barrier layer 3. This configuration isreferred to as first modification. It is to be noted that FIG. 3A is asectional view depicting, for example, a portion indicated by referencecharacter X in FIG. 3B in an enlarged scale.

In this case, since the source electrodes 7 are provided on the surfaceof the grooves 10 and the grooves 10 extend to the p-type back barrierlayer (here, p-GaN back barrier layer) 3, the source electrodes 7contact with the p-type back barrier layer 3. Consequently, thepotential of the p-type back barrier layer 3 can be made less likely tovary. Further, if a potential variation of the p-type back barrier layer3 is caused by electrification to the trap level or the like, then theon resistance or a threshold value varies. However, by adopting such astructure as described above, the potential variation of the p-type backbarrier layer 3 can be suppressed and stabilized operation can beimplemented.

The semiconductor device according to the first modification can befabricated in the following manner.

First, as depicted in FIG. 4A, an AlN nucleation layer as the bufferlayer 2, a p-GaN back barrier layer 3, a GaN electron transit layer 4and an AlGaN electron supply layer 5 (for example, Al_(0.2)Ga_(0.8)Nelectron supply layer) are formed on a SiC substrate 1 similarly as inthe embodiment described above. Consequently, the nitride semiconductorstacking structure 6 including the GaN channel layer 4 and the AlGaNelectron supply layer 5 is formed over the p-GaN back barrier layer 3.

Then, an element isolation region 11 is formed by performing, forexample, ion implantation of Ar so that the element isolation region 11is formed a round an active region 12 (refer to FIG. 3B). Here, the ionimplantation of Ar for formation of the element isolation region 11 maybe performed with energy of such a degree that ions reach the 2DEGregion of the interface between the AlGaN electron supply layer 5 andthe GaN channel layer 4.

Then, as depicted in FIG. 4B, a groove (etching region) 10 is formed ata location at which a source electrode is to be formed in the activeregion 12 so as to extend from the surface of the nitride semiconductorstacking structure 6, namely, from the surface of the AlGaN electronsupply layer 5, to the p-GaN back barrier layer 3, for example, byetching using chlorine-based gas.

After the groove 10 extending to the p-GaN back barrier layer 3 isformed in such a manner as just described, as an activation annealprocess for desorbing H from the p-GaN back barrier layer 3 to activatethe p-GaN back barrier layer 3, an anneal process is performed atapproximately 750° C. for approximately 10 minutes, for example, in anitrogen atmosphere. In this case, since the groove 10 extending to thep-GaN back barrier layer 3 is formed, H (hydrogen) can be desorbed fromthe p-GaN back barrier layer 3 through the groove 10. In particular, H(hydrogen) can be desorbed from the p-GaN back barrier layer 3 not onlythrough the side wall of the wafer (refer to FIG. 3B) but also throughthe groove 10 provided in the active region 12 at the inner side thanthe side wall 13. Consequently, the entire p-GaN back barrier layer 3can be activated with certainty also including a location spaced farfrom the side wall 13 of the wafer (for example, a central portion ofthe wafer; a central portion of the active region 12). Then, by thep-GaN back barrier layer 3 provided under the GaN channel layer 4 andactivated entirely, leak current flowing between the source electrode 7and the drain electrode 8 can be suppressed also where the gate lengthis short.

Then, as depicted in FIG. 4C, a source electrode 7 and a drain electrode8 are formed. Here, the source electrode 7 is formed on the groove 10extending to the p-GaN back barrier layer 3, namely, on the groove 10used for desorption of H from the p-GaN back barrier layer 3, so as toextend from the surface of the nitride semiconductor stacking structure6 (here, the surface of the AlGaN electron supply layer 5) to the bottomof the groove 10 and cover the surface of the groove 10, In other words,the source electrode 7 is formed over the groove 10 extending to thep-GaN back barrier layer 3. Further, the drain electrode 8 is formed onthe surface of the nitride semiconductor stacking structure 6 (here, thesurface of the AlGaN electron supply layer 5).

Thereafter, as depicted in FIG. 4D, a SiN film having a thickness of,for example, approximately 50 nm is formed as the passivation film 14for covering the surface, for example, by a CVD method.

Finally, the gate electrode 9 is formed after the SiN film 14 at alocation at which the gate electrode is to be formed is removed byetching, for example, using fluorine-based gas.

The semiconductor device according to the first modification can befabricated in this manner.

It is to be noted that, while the groove (etching region) 10 extendingto the p-type back barrier layer 3 in the first modification is providedjust under the source electrode 7, the embodiment is not limited tothis. For example, the groove (etching region) 10 extending to thep-type back barrier layer 3 may be provided just under the drainelectrode 8 or the groove (etching region) 10 extending to the p-typeback barrier layer 3 may be provided just under the source electrode 7and the drain electrode 8. In this case, the source electrode 7 or thedrain electrode 8 are provided, over the groove 10 extending to thep-type back barrier layer 3.

Further, while the groove 10 extending to the p-type back barrier layer3 in the embodiment described above is the groove 10 extending from thesurface of the nitride semiconductor stacking structure 6 to the p-typeback barrier layer 3, the embodiment is not limited to this.

For example, as depicted in FIG. 5, the groove 10 extending to thep-type back barrier layer 3 may be a groove (etching region) 10extending from the back face of the substrate 1 to the p-type backbarrier layer 3. By this, the heat radiation area can be provided wideand the heat radiation effect can be enhanced. This is referred to assecond modification.

The semiconductor device according to the second modification can befabricated in the following manner.

First, as depicted in FIG. 6A, an AlN nucleation layer as the bufferlayer 2, a p-GaN back barrier layer 3, a GaN electron transit layer 4and an AlGaN electron supply layer 5 (for example, Al_(0.2)Ga_(0.8)Melectron supply layer) are formed on a SiC substrate 1 similarly as inthe embodiment described above. Consequently, a nitride semiconductorstacking structure 6 including the GaN channel layer 4 and the AlGaNelectron supply layer 5 is formed over the p-GaN back barrier layer 3.

Then, as depicted in FIG. 6B, an element isolation region 11 is formedby ion implantation of, for example, Ar similarly as in the embodimentdescribed above.

Then, as depicted in FIG. 6C, by etching using, for example, inactivegas or chlorine-based gas, a groove (etching region) 10 is formed so asto extend from the back face of the substrate 1 to the p-GaN backbarrier layer 3.

After the groove 10 extending to the p-GaN back barrier layer 3 isformed in such a manner as just described, as an activation annealprocess for desorbing H from the p-GaN back barrier layer 3 to activatethe p-GaN back barrier layer 3, an anneal process is performed atapproximately 750° C. for approximately 10 minutes, for example, in anitrogen atmosphere. In this case, since the groove 10 extending to thep-GaN back barrier layer 3 is formed, H (hydrogen) can be desorbed fromthe p-GaN back, barrier layer 3 through the groove 10. In particular, H(hydrogen) can be desorbed from the p-GaN back barrier layer 3 not onlythrough the side wail of the wafer (refer to FIG. 3B) but also throughthe groove 10 provided at the inner side than the side wall 13.Consequently, the entire p-GaN back barrier layer 3 can be activatedwith certainty also including a location spaced far from the side wall13 of the wafer without performing a complicated process. Then, by thep-GaN back barrier layer 3 provided under the GaN channel layer 4 andactivated entirely, leak current flowing between the source electrode 7and the drain electrode 8 can be suppressed also where the gate lengthis short.

Thereafter, as depicted in FIG. 6D, a SiN film having a thickness of,for example, approximately 50 nm is formed as the passivation film 14for covering the surface, for example, by a CVD method.

Finally, after the SiN film 14 at a location at which the electrodes areto be formed is removed by etching, for example, using fluorine-basedgas, a source electrode 7, a drain electrode 8 and a gate electrode 9are formed on the surface of the nitride semiconductor stackingstructure 6 (here, on the surface of the AlGaN electron supply layer 5).

The semiconductor device according to the second embodiment can befabricated in such a manner as described above.

Further, while the anneal process for desorbing hydrogen from the p-typeback barrier layer 3 through the groove 10 extending to the p-GaN backbarrier layer 3 to activate the p-type back barrier layer 3 is performedin the embodiment described above, the embodiment is not limited tothis.

For example, before the anneal process is performed as depicted in FIG.7 after the groove 10 extending to the p-GaN back barrier layer 3 isformed, the hydrogen occlusion alloy 15 may be provided on the groove 10extending to the p-GaN back barrier layer 3, and at the step ofperforming the anneal process, hydrogen may be desorbed from the p-typeback barrier layer 3 using the groove 10 extending to the p-GaN backbarrier layer 3 and the hydrogen occlusion alloy 15 provided on thegroove 10 to activate the p-type back barrier layer 3. In other words,the activation anneal of the p-GaN back barrier layer 3 may beaccelerated using the hydrogen occlusion alloy 15. In this case, it ispreferable, for the hydrogen occlusion alloy 15 to include any one ofTi, Zr, Pd and Mg, This is referred to as third modification.

The semiconductor device according to the third modification can befabricated in the following manner.

First, as depicted in FIG. 8A, an AlN nucleation layer as the bufferlayer 2, a p-GaN back barrier layer 3, a GaN electron transit layer 4and an AlGaN electron supply layer 5 (for example, Al_(0.2)Ga_(0.8)Nelectron supply layer) are formed on a SiC substrate 1 similarly as inthe embodiment described above. Consequently, a nitride semiconductorstacking structure 6 including the GaN channel layer 4 and the AlGaNelectron supply layer 5 is formed over the p-GaN back barrier layer 3.

Then, as depicted in FIG. 8B, an element isolation region 11 is formedby ion implantation of, for example, Ar similarly as in the embodimentdescribed above.

Then, as depicted in FIG. 8C, by etching using, for example,chlorine-based gas, a groove (etching region) 10 is formed in theelement isolation region 11 in the proximity of the active region 12 soas to extend from the surface of the nitride semiconductor stackedstructure 6, namely, from the surface of the AlGaN electron supply layer5, to the p-GaN back barrier layer 3.

Then, as depicted in FIG. 8D, Ti that is the hydrogen occlusion alloy 15is deposited on the groove 10 extending to the p-GaN back barrier layer3.

After Ti that is the hydrogen occlusion alloy 15 is deposited on thegroove 10 extending to the p-GaN back barrier layer 3 in this manner, asthe activation anneal process for desorbing H from the p-GaN backbarrier layer 3 to activate the p-GaN back barrier layer 3, an annealprocess is performed at approximately 750° C. for approximately 10minutes, for example, in a nitrogen atmosphere. In this case, since thegroove 10 extending to the p-GaN back barrier layer 3 is formed and thehydrogen occlusion alloy 15 is provided on the groove 10, H (hydrogen)can be desorbed from the p-GaN back barrier layer 3 using the groove 10and the hydrogen occlusion alloy 15. In particular, H (hydrogen) can bedesorbed from the p-GaN back barrier layer 3 using not only the sidewall 13 of the wafer but also the groove 10 provided at the inner sidethan the side wall 13. Consequently, the entire p-GaN back barrier layer3 can be activated with certainty also including a location spaced farfrom the side wall 13 of the wafer. Further, since Ti that functions asthe hydrogen occlusion alloy 15 exists in the groove 10, desorption of Hfrom the p-GaN back barrier layer 3 can be accelerated and theactivation efficiency of the p-GaN back barrier layer 3 can be enhanced.Then, by the p-GaN back barrier layer 3 provided under the GaN channellayer 4 and activated entirely so that the activation efficiency isfurther enhanced, leak current flowing between the source electrode 7and the drain electrode 8 can be suppressed also where the gate lengthis short,

Ti that is the hydrogen occlusion alloy 15 is removed, for example, byfluoric acid after the activation anneal process is performed in such amanner as described above,

Thereafter, as depicted in FIG. 8E, similarly as in the embodimentdescribed above, a SiN film having a thickness of, for example,approximately 50 nm is formed as the passivation film 14 for coveringthe surface, for example, by a CVD method.

Finally, similarly as in the embodiment described above, after the SiNfilm 14 at a location at which the electrodes are to be formed isremoved by etching, for example, using fluorine-based gas, a sourceelectrode 7, a drain electrode 8 and a gate electrode 3 are formed onthe surface of the nitride semiconductor stacking structure 6 (here, thesurface of the AlGaN electron supply layer 5).

The semiconductor device according to the third modification can befabricated in such a manner as described above.

It is to be noted that, while the third modification is described as amodification to the embodiment described above, the present modificationcan be applied also to the other modifications such as the firstmodification and the second modification described above.

Second Embodiment

Now, a semiconductor device, a fabrication method for a semiconductordevice and a power supply apparatus according to a second embodiment aredescribed with reference to FIGS. 12 and 13.

The semiconductor device according to the present embodiment is asemiconductor package including, as a semiconductor chip, asemiconductor device (AlGaN/GaN-HEMT) according to any one of the firstembodiment and the modifications described above. It is to be noted thatthe semiconductor chip is referred to also as HEMT chip or transistorchip.

The second embodiment is described below taking a discrete package as anexample.

As depicted in FIG. 12, the present semiconductor device includes astage 30 on which a semiconductor chip 34 according to one of the firstembodiment and the modifications described above therein is mounted, agate lead 37, a source lead 39, a drain lead 38, bonding wires 36 (here,Al wires) and an encapsulation resin 40. It is to be noted that theencapsulation resin is referred to sometimes as a molding resin.

A gate pad 31, a source pad 32 and a drain pad 33 of the semiconductorchip 34 mounted on the stage 30 are coupled with the gate lead 37,source lead 39 and drain lead 38, respectively, by the Al wires 36,which then undergoes resin encapsulation.

Here, the stage 30 to which the back face of the substrate of thesemiconductor chip 34 is fixed by die attach material 35 (here, solder)is coupled electrically with the drain lead 38. It is to be noted thatthe embodiment is not limited to this, and the stage 30 may be coupledelectrically with the source lead 39.

How, a fabrication method for a semiconductor device (discrete package)according to the present embodiment is described.

First, a semiconductor chip 34 (AlGaN/GaN-HEMT) according to one of thefirst embodiment and the modifications described above is fixed to thestage 30 of a lead frame using, for example, die attach material 35(here, solder).

Then, by bonding using, for example, Al wires 36, the gate pad 31, drainpad 33 and source pad 32 of the semiconductor chip 34 are coupled withthe gate lead 37, drain lead 38 and source lead 39, respectively.

Thereafter, the lead frame is separated after resin encapsulation isperformed, for example, by a transfer mold method.

The semiconductor device (discrete package) can be fabricated in thismanner.

It is to be noted that, while the embodiment here is described taking,as an example, the discrete package in which the pads 31 to 33 of thesemiconductor chip 34 are used as bonding pads for wire bonding, theembodiment is not limited to this and some other semiconductor packagemay be used. For example, a semiconductor package may be used in whichpads of a semiconductor chip are used as bonding pads for wirelessbonding such as, for example, flip chip bonding. Further, a wafer levelpackage may be used. Further, a semiconductor package other than, adiscrete package may be used.

Now, a power supply apparatus that includes a semiconductor packageincluding an AlGaN/GaN-HEMT described above is described with referenceto FIG. 13.

The power supply apparatus is described below taking, as an example, acase in which an AlGaN/GaN-HEMT included in a semiconductor packagedescribed above is used for a PFC (power factor correction) circuitprovided in a power supply apparatus used for a server.

As depicted in FIG. 13, the present PFC circuit includes a diode bridge56, a choke coil 52, a first capacitor 54, an AlGaN/GaN-HEMT 51 includedin the semiconductor package described above, a diode 53 and a secondcapacitor 55.

Here, the present PFC circuit is configured by mounting the diode bridge56, choke coil 52, first capacitor 54, transistor 51 included in thesemiconductor package described above, diode 53 and second capacitor 55on a circuit board.

In the present embodiment, the drain lead 38, source lead 39 and gatelead 37 of the semiconductor package described above are inserted in adrain lead insertion portion, a source lead insertion portion and a gatelead insertion portion of the circuit board, respectively, and arefixed, for example, by solder or the like. The transistor 51 included inthe semiconductor package described above is coupled with the PFCcircuit formed on the circuit board in this manner.

Further, in the present PFC circuit, one of terminals of the choke coil52 and an anode terminal of the diode 53 are connected to a drainelectrode D of the AlGaN/GaN-HEMT 51. Further, one of terminals of thefirst capacitor 54 is connected to the other one of the terminals of thechoke coil 52, and one of terminals of the second capacitor 55 isconnected to a cathode terminal of the diode 53. Further, the other oneof the terminal of the first capacitor 54, a source electrode S of theAlGaN/GaN-HEMT 51 and the other one of the terminals of the secondcapacitor 55 are grounded. Further, a pair of terminals of the diodebridge 56 are connected to the opposite terminals of the first capacitor54, and an input terminal to which an alternating current (AC) voltageis inputted is connected to a different pair of terminals of the diodebridge 56. Further, the opposite terminals of the second capacitor 55are connected to output terminals from which a direct current (DC)voltage is outputted. A gate driver not depicted is connected to a gateelectrode G of the AlGaN/GaN-HEMT 51. In the present PFC circuit, bydriving the AlGaN/GaN-HEMT 51 by the gate driver, an AC voltage inputtedfrom the input terminal is converted into a DC voltage and thenoutputted from the output terminals.

Accordingly, with the power supply apparatus according to the presentembodiment, there is an advantage that the reliability can be enhanced.In particular, there is an advantage that, since the semiconductor chip34 according to any one of the first embodiment and the modificationsdescribed above is provided, a power supply apparatus having highreliability can be constructed.

It is to be noted that, while the embodiment is described here taking,as an example, a case in which the semiconductor device describedhereinabove (AlGaN/GaN-HEMT or a semiconductor package including theAlGaN/GaN-HEMT) is used for the PFC circuit provided in the power supplyapparatus to be used for a server, the embodiment is not limited tothis. For example, the semiconductor device described above(AlGaN/GaN-HEMT or a semiconductor package including the AlGaN/GaN-HEMT)may be used for electronic equipment (electronic apparatus) such as acomputer other than a server. Further, the semiconductor devicedescribed above (semiconductor package) may be used for other circuits(for example, a DC-DC converter or the like) provided in a power supplyapparatus.

Third Embodiment

Now, a high-frequency amplifier according to a third embodiment isdescribed with reference to FIG. 14.

The high-frequency amplifier according to the present embodiment is ahigh-frequency amplifier (high-output power amplifier) including asemiconductor device according to any one of the first embodiment andthe modifications described above.

As depicted in FIG. 14, the present high-frequency amplifier includes adigital pre-distortion circuit 41, mixers 42 a and 42 b and a poweramplifier 43. It is to be noted that the power amplifier is referred tosometimes simply as amplifier.

The digital pre-distortion circuit 41 compensates for a non-lineardistortion of an input signal.

The mixers 42 a and 42 b perform mixing of the input signal whosenon-linear distortion is compensated for and an alternating currentsignal.

The power amplifier 43 amplifies the input signal after mixing with thealternating current signal and includes a semiconductor device accordingto any one of the first embodiment and the modifications describedabove, namely, a semiconductor chip including an AlGaN/GaN-HEMT. It isto be noted that the semiconductor chip is referred to sometimes as HEMTchip or transistor chip.

It is to be noted that a configuration is depicted in FIG. 14 in which,for example, by changeover of a switch, a signal at the output side canbe mixed with an alternating current signal by the mixer 42 b and sentout to the digital pre-distortion circuit 41.

Accordingly, with the high-frequency amplifier according to the presentembodiment, there is an advantage that, since the semiconductor deviceaccording to any one of the first embodiment and the modificationsdescribed above is applied to the power amplifier 43, a high-frequencyamplifier having high reliability can be implemented.

All examples and conditional language provided herein are intended forthe pedagogical purposes of aiding the reader in understanding theinvention and the concepts contributed by the inventor to further theart, and are not to be construed as limitations to such specificallyrecited examples and conditions, nor does the organization of suchexamples in the specification relate to a showing of the superiority andinferiority of the invention. Although one or more embodiments of thepresent invention have been described in detail, it should be understoodthat the various changes, substitutions, and alterations could be madehereto without departing from the spirit and scope of the invention.

What is claimed is:
 1. A semiconductor device, comprising: a p-type backbarrier layer provided over a substrate and formed from a p-type nitridesemiconductor in which Mg or Zn is doped; a nitride semiconductorstacked structure provided over the p-type back barrier layer, thenitride semiconductor stacked structure including an electron transitlayer and an electron supply layer; a source electrode, a drainelectrode and a gate electrode provided, over the nitride semiconductorstacked structure; and a groove extending to the p-type back barrierlayer.
 2. The semiconductor device according to claim 1, wherein thegroove extends from the surface of the nitride semiconductor stackedstructure to the p-type back barrier layer.
 3. The semiconductor deviceaccording to claim 1, wherein the groove is provided in an active regionor in the proximity of the active region.
 4. The semiconductor deviceaccording to claim 1, wherein the groove functions also as an elementisolation groove.
 5. The semiconductor device according to claim 1,wherein the groove is provided in an element isolation region.
 6. Thesemiconductor device according to claim 1, wherein the source electrodeor the drain electrode is provided over the groove.
 7. The semiconductordevice according to claim 1, wherein the groove extends from the backface of the substrate to the p-type back barrier layer.
 8. Thesemiconductor device according to claim 1, wherein the p-type nitridesemiconductor is In_(x)Al_(y)Ga_((1−x−y))N (0≦x<1, 0≦y<1, 0<x+y≦1). 9.The semiconductor device according to claim 1, wherein the substrate isany one of a Si substrate, a SiC substrate, a sapphire substrate, a GaOsubstrate, an AlN substrate and a GaN substrate.
 10. The semiconductordevice according to claim 1, further comprising a passivation film tocover the surface of the groove.
 11. A power supply apparatus,comprising: a transistor; wherein the transistor includes: a p-type backbarrier layer provided over a substrate and formed from a p-type nitridesemiconductor in which Mg or Zn is doped; a nitride semiconductorstacked structure provided over the p-type back barrier layer, thenitride semiconductor stacked structure including an electron transitlayer and an electron supply layer; a source electrode, a drainelectrode and a gate electrode provided over the nitride semiconductorstacked structure, and a groove extending to the p-type back barrierlayer.
 12. A high-frequency amplifier, comprising: an amplifier toamplify an input signal; the amplifier to include a transistor; thetransistor including: a p-type back barrier layer provided over asubstrate and formed from a p-type nitride semiconductor in which Mg orZn is doped; a nitride semiconductor stacked structure provided over thep-type back barrier layer, the nitride semiconductor stacked structureincluding an electron transit layer and an electron supply layer; asource electrode, a drain electrode and a gate electrode provided overthe nitride semiconductor stacked structure; and a groove extending tothe p-type back barrier layer.
 13. A fabrication method for asemiconductor device, comprising: forming a p-type back barrier layerfrom a p-type nitride semiconductor in which Mg or Zn is doped over asubstrate; forming a nitride semiconductor stacked structure includingan electron transit layer and an electron supply layer over the p-typeback barrier layer; forming a source electrode, a drain electrode and agate electrode over the nitride semiconductor stacked structure; forminga groove extending to the p-type back barrier layer; and performing ananneal process for desorbing hydrogen from the p-type back barrier layerthrough the groove to activate the p-type back barrier layer.
 14. Thefabrication method for a semiconductor device according to claim 13,further comprising providing a hydrogen occlusion alloy in the groovebefore the anneal process is performed after the groove is formed;wherein in the performing the anneal process, hydrogen is desorbed fromthe p-type back barrier layer using the groove and the hydrogenocclusion alloy formed in the groove to activate the hydrogen occlusionalloy.
 15. The fabrication method for a semiconductor device accordingto claim 14, wherein the hydrogen, occlusion, allay contains any one ofTi, Zr, Pd and Mg.
 16. The fabrication method for a semiconductor deviceaccording to claim 13, wherein, in the forming the groove, the groove isformed so as to extend from the surface of the nitride semiconductorstacked structure to the p-type back barrier layer.
 17. The fabricationmethod for a semiconductor device according to claim 13, wherein, in theforming the groove, the groove is formed in an active region or in theproximity of the active region.
 18. The fabrication method for asemiconductor device according to claim 13, wherein, in the forming thesource electrode, drain electrode and gate electrode, the sourceelectrode or the drain electrode is formed over the groove.
 19. Thefabrication method for a semiconductor device according to claim 13,wherein, in the forming the groove, the groove is formed so as to extendfrom the back face of the substrate to the p-type back barrier layer.